Techniques for Yield Enhancement of VLSI Adders 1

For VLSI application-speciic arrays and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modiications. In this paper, we compare these two yield enhancement approaches by using adders as an example. Our yield projections indicate that the layout modiication technique is more eecient when the defect density is low, while reconnguration is more eecient for a high defect density. However, from the point of the view of eeective yield, the layout modiication is superior to defect tolerance in the practical range of defect density.